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    Low power device for high-speed time-interleaved sampling
    1.
    发明授权
    Low power device for high-speed time-interleaved sampling 有权

    公开(公告)号：US10911060B1

    公开(公告)日：2021-02-02

    申请号：US16683854

    申请日：2019-11-14

    Applicant: Xilinx, Inc.

    Inventor： Pedro W. Neto ,  Ronan Casey ,  Declan Carey

    IPC: H03M1/00 ,  H03M1/46 ,  G11C27/02 ,  H03M1/06 ,  H03M1/16

    Abstract: Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi≥1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi≥1, at least one buffer of the Xi buffers may include an integrating buffer, N≥i≥1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.

    Circuits for and methods of controlling output swing in a current-mode logic circuit
    2.
    发明授权
    Circuits for and methods of controlling output swing in a current-mode logic circuit 有权
    在电流模式逻辑电路中控制输出摆幅的电路和方法

    公开(公告)号：US09209809B1

    公开(公告)日：2015-12-08

    申请号：US14573815

    申请日：2014-12-17

    Applicant: Xilinx, Inc.

    Inventor： Kevin Geary ,  Ronan Casey ,  Declan Carey ,  Thomas Mallard

    IPC: H03K19/094 ,  H03K19/0185 ,  H03K19/003

    CPC classification number: H03K19/018514 ,  H03K19/00384

    Abstract: A circuit for controlling output swing in a current-mode logic circuit is described. The circuit comprises a plurality of current-mode logic circuits coupled in series; a first current-mode logic circuit of the plurality of current-mode logic circuits coupled to provide a signal to a second current-mode logic circuit of the plurality of current-mode logic circuits; an amplitude detector coupled to detect an amplitude of the signal received at the second current-mode logic circuit; and a control circuit coupled to the amplitude detector; wherein the control circuit generates an amplitude control signal for a current-mode logic circuit of the plurality of current-mode logic circuits based upon a detected amplitude of the signal received at the second current-mode logic circuit. A method of controlling output swing in a current-mode logic circuit is also disclosed.

    Abstract translation: 描述用于控制电流模式逻辑电路中的输出摆幅的电路。 电路包括串联耦合的多个电流模式逻辑电路; 所述多个电流模式逻辑电路中的第一电流模式逻辑电路被耦合以向所述多个电流模式逻辑电路中的第二电流模式逻辑电路提供信号; 振幅检测器，被耦合以检测在第二电流模式逻辑电路处接收的信号的幅度; 以及耦合到所述幅度检测器的控制电路; 其中所述控制电路基于在所述第二电流模式逻辑电路处接收的所述信号的检测幅度，生成所述多个电流模式逻辑电路中的电流模式逻辑电路的幅度控制信号。 还公开了一种控制电流模式逻辑电路中的输出摆幅的方法。

    Windowing for high-speed analog-to-digital conversion
    3.
    发明授权
    Windowing for high-speed analog-to-digital conversion 有权
    用于高速模数转换的窗口

    公开(公告)号：US08970419B2

    公开(公告)日：2015-03-03

    申请号：US13928798

    申请日：2013-06-27

    Applicant: Xilinx, Inc.

    Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

    IPC: H03M1/34 ,  H03M1/12

    CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

    Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

    Abstract translation: 一个模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

    WINDOWING FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION
    6.
    发明申请
    WINDOWING FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION 有权
    WINDOWING用于高速模拟数字转换

    公开(公告)号：US20150002326A1

    公开(公告)日：2015-01-01

    申请号：US13928798

    申请日：2013-06-27

    Applicant: Xilinx, Inc.

    Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

    IPC: H03M1/12

    CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

    Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

    Abstract translation: 公开了一种模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

    Inductor-less divide-by-3 injection locked frequency divider
    7.
    发明授权
    Inductor-less divide-by-3 injection locked frequency divider 有权

    公开(公告)号：US10715150B1

    公开(公告)日：2020-07-14

    申请号：US16274145

    申请日：2019-02-12

    Applicant: Xilinx, Inc.

    Inventor： Declan Carey

    IPC: H03B19/12 ,  H03K21/10 ,  H03K21/02

    Abstract: A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.

    Continuous time linear equalization
    8.
    发明授权
    Continuous time linear equalization 有权

    公开(公告)号：US10263815B1

    公开(公告)日：2019-04-16

    申请号：US15837928

    申请日：2017-12-11

    Applicant: Xilinx, Inc.

    Inventor： Kevin Geary ,  Declan Carey ,  Mohamed Elzeftawi

    IPC: H04L25/03 ,  H03G3/30 ,  H03K19/177

    Abstract: This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.

    High-speed analog comparator
    9.
    发明授权
    High-speed analog comparator 有权
    高速模拟比较器

    公开(公告)号：US09007096B1

    公开(公告)日：2015-04-14

    申请号：US14324858

    申请日：2014-07-07

    Applicant: Xilinx, Inc.

    Inventor： Declan Carey ,  Thomas Mallard ,  Mark Smyth ,  James Hudner

    IPC: H03K5/22 ,  G01R17/02

    CPC classification number: H03K5/2481 ,  H03F3/45197 ,  H03F2200/78 ,  H03F2203/45674

    Abstract: An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.

    Abstract translation: 一般涉及电压转换的装置包括耦合以接收输入电压和参考电压的放大器。 第一和第二转换器耦合到放大器以接收偏置电压。 第一转换器包括耦合以接收偏置电压以调整第一尾电流的第一跨导器和第一差分输入。 第一转换器的第一反相器具有耦合输入到输出的第一反馈器件，以提供第一跨阻抗放大器负载。 第一反相器耦合到第一跨导器。 第二转换器包括耦合以接收偏置电压以调整第二尾电流的第二跨导器和第二差分输入。 第二转换器的第二反相器具有耦合输入到输出以提供第二跨阻放大器负载的第二反馈装置。 第二反相器耦合到第二跨导器。

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