Invention Grant
- Patent Title: Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks
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Application No.: US16151171Application Date: 2018-10-03
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Publication No.: US10922461B2Publication Date: 2021-02-16
- Inventor: Mahesh A. Iyer , Vasudeva M. Kamath
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/3312 ; G06F30/34 ; G06F30/327 ; G06F30/398 ; G06F119/12

Abstract:
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the register retiming of registers in the system driven by a different clock.
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