Invention Grant
- Patent Title: Semiconductor package having integrated stiffener region
-
Application No.: US16328231Application Date: 2016-09-14
-
Publication No.: US10923415B2Publication Date: 2021-02-16
- Inventor: Eng Huat Goh , Jiun Hann Sir , Min Suet Lim , Shawna M. Liff , Feras Eid
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Eversheds Sutherland (US) LLP
- International Application: PCT/US2016/051697 WO 20160914
- International Announcement: WO2018/052413 WO 20180322
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/552 ; H01L23/00 ; H01L21/48 ; H01L23/538

Abstract:
Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
Public/Granted literature
- US20190214338A1 SEMICONDUCTOR PACKAGE HAVING INTEGRATED STIFFENER REGION Public/Granted day:2019-07-11
Information query
IPC分类: