利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

105 条记录 (耗时 0.024 秒)

    Wrappable EMI shields
    2.
    发明授权
    Wrappable EMI shields 有权

    公开(公告)号：US11699664B2

    公开(公告)日：2023-07-11

    申请号：US17089756

    申请日：2020-11-05

    申请人： Intel Corporation

    发明人： Eng Huat Goh ,  Tin Poay Chuah ,  Yew San Lim ,  Min Suet Lim

    IPC分类号： H01L23/552 ,  H05K3/28 ,  H05K1/02

    CPC分类号： H01L23/552 ,  H05K1/0209 ,  H05K3/284

    摘要： According to the various aspects, the present device includes a printed circuit board having a top surface and a bottom surface, with a plurality of semiconductor devices coupled to the top surface and a flexible electromagnetic shield wrap conformally positioned over and between the plurality of semiconductor devices and the top surface of the printed circuit board. The flexible electromagnetic shield wrap is conformally positioned by applying a vacuum and is removable after the vacuum seal is broken.

    Semiconductor package having integrated stiffener region
    4.
    发明授权
    Semiconductor package having integrated stiffener region 有权

    公开(公告)号：US10923415B2

    公开(公告)日：2021-02-16

    申请号：US16328231

    申请日：2016-09-14

    申请人： Intel Corporation

    发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Shawna M. Liff ,  Feras Eid

    IPC分类号： H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538

    摘要： Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.

    Capacitive interconnect in a semiconductor package
    5.
    发明授权
    Capacitive interconnect in a semiconductor package 有权

    公开(公告)号：US10609813B2

    公开(公告)日：2020-03-31

    申请号：US15182091

    申请日：2016-06-14

    申请人： Intel Corporation

    发明人： Eng Huat Goh ,  Min Suet Lim ,  Fern Nee Tan ,  Khang Choong Yong ,  Jiun Hann Sir

    IPC分类号： H05K1/14 ,  H01L23/498 ,  H01G4/33 ,  H01G4/228 ,  H01G4/12 ,  H05K1/02 ,  H01L21/48 ,  H01L23/50

    摘要： Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.

    Board to board interconnect
    8.
    发明授权
    Board to board interconnect 有权

    公开(公告)号：US10356902B2

    公开(公告)日：2019-07-16

    申请号：US14757984

    申请日：2015-12-26

    申请人： INTEL CORPORATION

    发明人： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

    IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K1/14

    摘要： A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

    Three capacitor stack and associated methods
    10.
    发明授权
    Three capacitor stack and associated methods 有权

    公开(公告)号：US09960224B2

    公开(公告)日：2018-05-01

    申请号：US15282504

    申请日：2016-09-30

    申请人： Intel Corporation

    发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Han Kung Chua ,  Min Suet Lim ,  Hoay Tien Teoh

    IPC分类号： H01L49/02

    CPC分类号： H01L28/75

    摘要： A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.