Invention Grant
- Patent Title: Reduced uncorrectable memory errors
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Application No.: US16444480Application Date: 2019-06-18
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Publication No.: US10936418B2Publication Date: 2021-03-02
- Inventor: Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; H03M13/05 ; H03M13/27 ; H03M13/00 ; G06F3/06 ; H03M13/15 ; H03M13/19
Abstract:
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
Information query
