Invention Grant
- Patent Title: Method for fabricating transistor with thinned channel
-
Application No.: US16526898Application Date: 2019-07-30
-
Publication No.: US10937907B2Publication Date: 2021-03-02
- Inventor: Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/78 ; H01L29/423 ; H01L29/66 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/161 ; H01L29/165 ; H01L29/24 ; H01L29/267 ; H01L29/49 ; H04B1/3827
Abstract:
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Information query
IPC分类:
