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144 条记录 (耗时 0.026 秒)

    Dynamic random access memory including threshold switch
    3.
    发明授权
    Dynamic random access memory including threshold switch 有权

    公开(公告)号：US11031072B2

    公开(公告)日：2021-06-08

    申请号：US16641574

    申请日：2017-09-28

    申请人： Intel Corporation

    发明人： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Prashant Majhi

    IPC分类号： G11C11/00 ,  G11C11/56 ,  H01L45/00 ,  H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/4096 ,  H01L27/108 ,  G11C14/00 ,  G11C11/40

    摘要： Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

    Ferroelectric field-effect transistor devices having a top gate and a bottom gate
    4.
    发明授权
    Ferroelectric field-effect transistor devices having a top gate and a bottom gate 有权

    公开(公告)号：US10937807B2

    公开(公告)日：2021-03-02

    申请号：US16465044

    申请日：2016-12-29

    申请人： INTEL CORPORATION

    发明人： Brian S. Doyle ,  Kaan Oguz ,  Ricky J. Tseng ,  Kevin P. O'Brien

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1159 ,  G11C5/06

    摘要： Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

    Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer
    6.
    发明授权
    Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer 有权

    公开(公告)号：US10707409B2

    公开(公告)日：2020-07-07

    申请号：US15882546

    申请日：2018-01-29

    申请人： INTEL CORPORATION

    发明人： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

    IPC分类号： H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

    摘要： Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.