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1.
公开(公告)号:US20220344376A1
公开(公告)日:2022-10-27
申请号:US17864264
申请日:2022-07-13
申请人: Intel Corporation
发明人: Aaron D. Lilak , Anh Phan , Patrick Morrow , Willy Rachmady , Gilbert Dewey , Jessica M. Torres , Kimin Jun , Tristan A. Tronic , Christopher J. Jezewski , Hui Jae Yoo , Robert S. Chau , Chi-Hwa Tsang
IPC分类号: H01L27/12 , H01L21/02 , H01L21/285 , H01L21/84 , H01L27/22 , H01L27/24 , H01L29/08 , H01L29/16 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/78
摘要: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.
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2.
公开(公告)号:US11430814B2
公开(公告)日:2022-08-30
申请号:US16957047
申请日:2018-03-05
申请人: Intel Corporation
发明人: Aaron D. Lilak , Anh Phan , Patrick Morrow , Willy Rachmady , Gilbert Dewey , Jessica M. Torres , Kimin Jun , Tristan A. Tronic , Christopher J. Jezewski , Hui Jae Yoo , Robert S. Chau , Chi-Hwa Tsang
IPC分类号: H01L27/12 , H01L21/02 , H01L21/285 , H01L21/84 , H01L27/22 , H01L27/24 , H01L29/08 , H01L29/16 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/78
摘要: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.
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公开(公告)号:US10897009B2
公开(公告)日:2021-01-19
申请号:US16414956
申请日:2019-05-17
申请人: INTEL CORPORATION
发明人: Niloy Mukherjee , Ravi Pillarisetty , Prashant Majhi , Uday Shah , Ryan E Arch , Markus Kuhn , Justin S. Brockman , Huiying Liu , Elijah V Karpov , Kaan Oguz , Brian S. Doyle , Robert S. Chau
IPC分类号: H01L45/00
摘要: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
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公开(公告)号:US10832847B2
公开(公告)日:2020-11-10
申请号:US15735622
申请日:2015-06-26
申请人: Intel Corporation
发明人: Brian S. Doyle , Kaan Oguz , Kevin P. O'Brien , David L. Kencke , Charles C. Kuo , Mark L. Doczy , Satyarth Suri , Robert S. Chau
IPC分类号: H01L43/02 , H01L43/08 , H01L43/10 , H01F10/193 , H01F10/32
摘要: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.
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公开(公告)号:US10832749B2
公开(公告)日:2020-11-10
申请号:US15735625
申请日:2015-06-26
申请人: Intel Corporation
发明人: Charles C. Kuo , Justin S. Brockman , Juan G. Alzate Vinasco , Kaan Oguz , Kevin P. O'Brien , Brian S. Doyle , Mark L. Doczy , Satyarth Suri , Robert S. Chau
摘要: An embodiment includes an apparatus including: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, including a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.
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公开(公告)号:US20190287789A1
公开(公告)日:2019-09-19
申请号:US16431646
申请日:2019-06-04
申请人: Intel Corporation
发明人: Sansaptak Dasgupta , Han Wui Then , Benjamin Chu-Kung , Marko Radosavljevic , Sanaz K. Gardner , Seung Hoon Sung , Ravi Pillarisetty , Robert S. Chau
IPC分类号: H01L21/02 , H01L29/78 , H01L29/778 , H01L29/267 , H01L29/20 , H01L29/16 , H01L29/06 , H01L29/04 , H01L27/06 , H01L21/8252
摘要: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
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公开(公告)号:US10340443B2
公开(公告)日:2019-07-02
申请号:US15735613
申请日:2015-06-26
申请人: Intel Corporation
发明人: Brian S. Doyle , Kaan Oguz , Kevin P. O'Brien , David L. Kencke , Elijah V. Karpov , Charles C. Kuo , Mark L. Doczy , Satyarth Suri , Robert S. Chau , Niloy Mukherjee , Prashant Majhi
摘要: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.
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公开(公告)号:US10056456B2
公开(公告)日:2018-08-21
申请号:US15526735
申请日:2014-12-18
申请人: INTEL CORPORATION
发明人: Han Wui Then , Sansaptak Dasgupta , Marko Radosavljevic , Seung Hoon Sung , Sanaz K. Gardner , Robert S. Chau
IPC分类号: H01L29/66 , H01L29/08 , H01L29/778 , H01L29/423 , H01L29/20
CPC分类号: H01L29/0847 , H01L29/2003 , H01L29/4236 , H01L29/42376 , H01L29/66462 , H01L29/7786
摘要: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.
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9.
公开(公告)号:US09923087B2
公开(公告)日:2018-03-20
申请号:US15410681
申请日:2017-01-19
申请人: Intel Corporation
发明人: Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Niti Goel , Sanaz Kabehie Gardner , Seung Hoon Sung , Ravi Pillarisetty , Robert S. Chau
IPC分类号: H01L29/66 , H01L29/778 , H01L29/205 , H01L21/311 , H01L21/02 , H01L21/265 , H01L21/223 , H01L29/08 , H01L29/20 , H01L29/207 , H01L29/423
CPC分类号: H01L29/7784 , H01L21/0254 , H01L21/2233 , H01L21/2236 , H01L21/2654 , H01L21/26546 , H01L21/31111 , H01L21/31144 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42376 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
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10.
公开(公告)号:US09922826B2
公开(公告)日:2018-03-20
申请号:US15527287
申请日:2014-12-17
申请人: Intel Corporation
发明人: Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Robert S. Chau , Sanaz K. Gardner , Seung Hoon Sung
IPC分类号: H01L21/02 , H01L29/20 , H01L29/225 , H01L29/205 , H01L29/32 , H01L29/08 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/8258 , H01L27/06 , H01L29/778 , H01L29/22 , H01L23/00 , H01L27/092
CPC分类号: H01L21/0265 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02551 , H01L21/02554 , H01L21/02557 , H01L21/0256 , H01L21/02562 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L21/0274 , H01L21/8258 , H01L23/48 , H01L24/16 , H01L25/065 , H01L27/0605 , H01L27/092 , H01L27/0922 , H01L29/0657 , H01L29/0688 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/2203 , H01L29/225 , H01L29/267 , H01L29/32 , H01L29/66462 , H01L29/66969 , H01L29/7786 , H01L2224/16227 , H01L2924/15311
摘要: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.
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