Invention Grant
- Patent Title: Semiconductor device and memory access control method
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Application No.: US16451915Application Date: 2019-06-25
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Publication No.: US10942802B2Publication Date: 2021-03-09
- Inventor: Yukitoshi Tsuboi , Hiroyuki Hamasaki
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2016-039566 20160302
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10

Abstract:
A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.
Public/Granted literature
- US20190317854A1 SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD Public/Granted day:2019-10-17
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