-
公开(公告)号：US10027900B2
公开(公告)日：2018-07-17
申请号：US15647522
申请日：2017-07-12
Applicant: Renesas Electronics Corporation
Inventor： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
IPC: G06K9/36 , G06K9/32 , G06K9/60 , H04N5/247 , G06T3/20 , H04N7/18 , B60R1/00 , G06T3/00 , H04N5/21 , G06T5/00
Abstract: Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.
-
2.发明申请公开(公告)号：US20170039677A1
公开(公告)日：2017-02-09
申请号：US15296539
申请日：2016-10-18
Applicant: Renesas Electronics Corporation
Inventor： Akihiro YAMAMOTO , Hiroyuki Hamasaki
CPC classification number: G06T3/0006 , G06K9/52 , G06K2009/4666 , G06T3/0087 , G06T3/40 , G06T3/60 , G06T5/006 , G06T7/60 , G06T7/73 , G06T2207/20172 , H04N7/18
Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.
Abstract translation: 半导体器件1包括图像输入单元11和图像输出单元12.图像输入单元11从相机91接收第一图像数据，并且通过共享总线130将第二图像数据输出到存储器93.图像输出单元 12通过共享总线130接收存储在存储器单元93中的第二图像数据，并将第三图像数据输出到监视器92.通过对第一图像数据进行仿射变换来生成第三图像数据。 在图像输入单元11中不进行仿射变换中的放大处理。这样，可以提供适合于图像处理等的优异的半导体装置。
-
公开(公告)号：US10104332B2
公开(公告)日：2018-10-16
申请号：US15961985
申请日：2018-04-25
Applicant: Renesas Electronics Corporation
Inventor： Hiroyuki Hamasaki , Atsushi Nakamura , Manabu Koike , Hideaki Kido , Nobuyasu Kanekawa
Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.
-
公开(公告)号：US20180059989A1
公开(公告)日：2018-03-01
申请号：US15806182
申请日：2017-11-07
Applicant: Renesas Electronics Corporation
Inventor： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F9/30087 , G06K9/00805
Abstract: Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.
-
公开(公告)号：US09836247B2
公开(公告)日：2017-12-05
申请号：US15157310
申请日：2016-05-17
Applicant: Renesas Electronics Corporation
Inventor： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F9/30087 , G06K9/00805
Abstract: Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.
-
Patent Agency Ranking
公开(公告)号：US20160255280A1
公开(公告)日：2016-09-01
申请号：US15149143
申请日：2016-05-08
Applicant: Renesas Electronics Corporation
Inventor： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
CPC classification number: H04N5/247 , B60R1/00 , B60R2300/60 , G06T3/00 , G06T3/20 , G06T5/006 , G06T2207/10016 , G06T2207/20172 , G06T2207/30252 , H04N5/21 , H04N7/18
Abstract: Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.
-
7.发明授权公开(公告)号：US11036662B2
公开(公告)日：2021-06-15
申请号：US16806759
申请日：2020-03-02
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kyohei Yamaguchi , Daisuke Kawakami , Hiroyuki Hamasaki
Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.
-
公开(公告)号：US10511799B2
公开(公告)日：2019-12-17
申请号：US16133351
申请日：2018-09-17
Applicant: Renesas Electronics Corporation
Inventor： Hiroyuki Hamasaki , Atsushi Nakamura , Manabu Koike , Hideaki Kido , Nobuyasu Kanekawa
Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.
-
公开(公告)号：US10387995B2
公开(公告)日：2019-08-20
申请号：US15647805
申请日：2017-07-12
Applicant: Renesas Electronics Corporation
Inventor： Akihiro Yamamoto , Hiroyuki Hamasaki
IPC: G06T3/00 , G06K9/52 , G06T3/40 , G06T5/00 , G06T7/60 , G06T7/73 , G06T3/60 , H04N7/18 , G06K9/46
Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.
-
公开(公告)号：US10379941B2
公开(公告)日：2019-08-13
申请号：US15446501
申请日：2017-03-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yukitoshi Tsuboi , Hiroyuki Hamasaki
Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.
-
-
-
-
-
-
-
-
-
Search Results
22
records
(took 0.018 seconds)
