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    Semiconductor device and memory access control method
    4.
    发明授权
    Semiconductor device and memory access control method 有权

    公开(公告)号：US10942802B2

    公开(公告)日：2021-03-09

    申请号：US16451915

    申请日：2019-06-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi Tsuboi ,  Hiroyuki Hamasaki

    IPC: G06F11/00 ,  G06F11/10

    Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

    Data processing device and data processing method
    5.
    发明授权
    Data processing device and data processing method 有权

    公开(公告)号：US10735028B2

    公开(公告)日：2020-08-04

    申请号：US16175567

    申请日：2018-10-30

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi Tsuboi

    IPC: H03M13/00 ,  H03M13/29 ,  H03M13/37 ,  H03M13/19 ,  G06F11/10

    Abstract: The subject is to improve the detection performance in the error detection of data using an ECC. A data processing device 1 includes an encoder device 2 that includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unit 5 to generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unit 4 generates the first ECC for the first data. The encoder unit 5 generates the second ECC for the second data obtained by permutating a bit of the first data.

    Semiconductor device, diagnostic test, and diagnostic test circuit
    6.
    发明授权
    Semiconductor device, diagnostic test, and diagnostic test circuit 有权

    公开(公告)号：US10520549B2

    公开(公告)日：2019-12-31

    申请号：US15800936

    申请日：2017-11-01

    Applicant: Renesas Electronics Corporation

    Inventor： Yukitoshi Tsuboi ,  Hideo Nagano ,  Hiroshi Nagaoka ,  Yusuke Matsunaga ,  Yutaka Igaku ,  Naotaka Kubota

    IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/08

    Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

    Abnormal interrupt request processing
    9.
    发明授权
    Abnormal interrupt request processing 有权

    公开(公告)号：US09678900B2

    公开(公告)日：2017-06-13

    申请号：US14328154

    申请日：2014-07-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takuya Hirade ,  Yukitoshi Tsuboi ,  Ryosuke Okuda

    IPC: G06F13/24 ,  G06F11/22

    CPC classification number: G06F13/24 ,  G06F11/2231 ,  G06F11/2273 ,  Y02D10/14

    Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

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