Invention Grant
- Patent Title: Electronic device packaging with galvanic isolation
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Application No.: US16102922Application Date: 2018-08-14
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Publication No.: US10943855B2Publication Date: 2021-03-09
- Inventor: Maria Cristina Estacio , Marlon Bartolo , Maria Clemens Ypil Quinones , Chung-Lin Wu
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/495 ; H01L23/00 ; H01L23/538

Abstract:
In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.
Public/Granted literature
- US20190067171A1 ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION Public/Granted day:2019-02-28
Information query
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