公开(公告)号：US11735508B2

公开(公告)日：2023-08-22

申请号：US17453623

申请日：2021-11-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome Teysseyre ,  Romel Manatad ,  Chung-Lin Wu ,  Bigildis Dosdos ,  Erwin Ian Almagro ,  Maria Cristina Estacio

IPC: H01L23/498 ,  H01L23/495

CPC classification number: H01L23/49827 ,  H01L23/495 ,  H01L23/49575 ,  H01L23/49586 ,  H01L2224/48137 ,  H01L2224/48247

Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

公开(公告)号：US12300583B2

公开(公告)日：2025-05-13

申请号：US18454970

申请日：2023-08-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erwin Ian Vamenta Almagro ,  Maria Clemens Ypil Quinones ,  Romel N. Manatad ,  Maria Cristina Estacio ,  Elsie Agdon Cabahug

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/522

Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

公开(公告)号：US11791247B2

公开(公告)日：2023-10-17

申请号：US17305396

申请日：2021-07-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erwin Ian Vamenta Almagro ,  Maria Clemens Ypil Quinones ,  Romel N. Manatad ,  Maria Cristina Estacio ,  Elsie Agdon Cabahug

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/49541 ,  H01L23/31 ,  H01L23/5226

Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

公开(公告)号：US10943855B2

公开(公告)日：2021-03-09

申请号：US16102922

申请日：2018-08-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina Estacio ,  Marlon Bartolo ,  Maria Clemens Ypil Quinones ,  Chung-Lin Wu

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/538

Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

公开(公告)号：US11984424B2

公开(公告)日：2024-05-14

申请号：US17158143

申请日：2021-01-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil Yoo ,  Maria Cristina Estacio ,  Jerome Teysseyre ,  Seungwon Im ,  JooYang Eom

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L24/92 ,  H01L21/56 ,  H01L23/49527 ,  H01L23/49575 ,  H01L23/52 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L23/3107 ,  H01L23/49513 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/73213 ,  H01L2224/73217 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/8384 ,  H01L2224/8484 ,  H01L2224/92142 ,  H01L2224/92144

Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

公开(公告)号：US10910297B2

公开(公告)日：2021-02-02

申请号：US16429366

申请日：2019-06-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome Teysseyre ,  Maria Cristina Estacio ,  Seungwon Im

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/433 ,  H01L23/473 ,  H01L23/00 ,  H01L29/16

Abstract: In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.

公开(公告)号：US12278169B2

公开(公告)日：2025-04-15

申请号：US17249529

申请日：2021-03-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina Estacio ,  Marlon Bartolo ,  Maria Clemens Ypil Quinones ,  Chung-Lin Wu

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/538

Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.

公开(公告)号：US12142551B2

公开(公告)日：2024-11-12

申请号：US18055139

申请日：2022-11-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome Teysseyre ,  Maria Cristina Estacio ,  Seungwon Im

IPC: H01L29/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/473 ,  H01L23/495

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

公开(公告)号：US11621203B2

公开(公告)日：2023-04-04

申请号：US16539319

申请日：2019-08-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina Estacio ,  Jerome Teysseyre ,  Elsie Agdon Cabahug

IPC: H01L23/31 ,  H01L29/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/495

Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.

公开(公告)号：US20210151367A1

公开(公告)日：2021-05-20

申请号：US17248541

申请日：2021-01-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome Teysseyre ,  Maria Cristina Estacio ,  Seungwon Im

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/433 ,  H01L23/473 ,  H01L23/00 ,  H01L29/16

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.