Invention Grant
- Patent Title: Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions
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Application No.: US16147109Application Date: 2018-09-28
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Publication No.: US10956813B2Publication Date: 2021-03-23
- Inventor: Ian A. Young , Ram Krishnamurthy , Sasikanth Manipatruni , Gregory K. Chen , Amrita Mathuriya , Abhishek Sharma , Raghavan Kumar , Phil Knag , Huseyin Ekin Sumbul
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06N3/06
- IPC: G06N3/06 ; G06N3/063 ; G11C11/419 ; G11C5/06 ; H03M7/30 ; G11C11/413 ; G11C7/10 ; G11C11/54 ; G06N3/04

Abstract:
An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.
Public/Granted literature
- US20190042928A1 COMPUTE-IN-MEMORY CIRCUIT HAVING A MULTI-LEVEL READ WIRE WITH ISOLATED VOLTAGE DISTRIBUTIONS Public/Granted day:2019-02-07
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