Invention Grant
- Patent Title: Layered super-reticle computing : architectures and methods
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Application No.: US16862263Application Date: 2020-04-29
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Publication No.: US10963022B2Publication Date: 2021-03-30
- Inventor: Simon C. Steely, Jr. , Richard Dischler , David Bach , Olivier Franza , William J. Butera , Christian Karl , Benjamin Keen , Brian Leung
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H05K1/18
- IPC: H05K1/18 ; G06F1/18 ; H01L23/538 ; G06F9/50 ; G06F15/76 ; H01L25/065

Abstract:
Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200371566A1 LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS Public/Granted day:2020-11-26
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