公开(公告)号：US20200371566A1

公开(公告)日：2020-11-26

申请号：US16862263

申请日：2020-04-29

Applicant: Intel Corporation

Inventor： Simon C. Steely, JR. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: G06F1/18 ,  H01L23/538 ,  G06F9/50 ,  H01L25/065 ,  G06F15/76

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11656662B2

公开(公告)日：2023-05-23

申请号：US17174106

申请日：2021-02-11

Applicant: Intel Corporation

Inventor： Simon C. Steely, Jr. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: G06F1/18 ,  H01L23/538 ,  G06F15/76 ,  H01L25/065 ,  G06F9/50

CPC classification number: G06F1/183 ,  G06F9/5027 ,  G06F15/76 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

公开(公告)号：US10963022B2

公开(公告)日：2021-03-30

申请号：US16862263

申请日：2020-04-29

Applicant: Intel Corporation

Inventor： Simon C. Steely, Jr. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: H05K1/18 ,  G06F1/18 ,  H01L23/538 ,  G06F9/50 ,  G06F15/76 ,  H01L25/065

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210255674A1

公开(公告)日：2021-08-19

申请号：US17174106

申请日：2021-02-11

Applicant: Intel Corporation

Inventor： Simon C. Steely, JR. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: G06F1/18 ,  H01L23/538 ,  G06F15/76 ,  H01L25/065 ,  G06F9/50

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

公开(公告)号：US10691182B2

公开(公告)日：2020-06-23

申请号：US16416753

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Simon C. Steely, Jr. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: H05K1/18 ,  G06F1/18 ,  H01L23/538 ,  G06F15/76 ,  H01L25/065 ,  G06F9/50

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190354146A1

公开(公告)日：2019-11-21

申请号：US16416753

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Simon C. Steely, JR. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: G06F1/18 ,  H01L23/538 ,  H01L25/065 ,  G06F9/50 ,  G06F15/76

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.