- 专利标题: Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture
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申请号: US16502141申请日: 2019-07-03
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公开(公告)号: US10963411B1公开(公告)日: 2021-03-30
- 发明人: Martin L. Voogel , Trevor J. Bauer , Rafael C. Camarota
- 申请人: XILINX, INC.
- 申请人地址: US CA San Jose
- 专利权人: XILINX, INC.
- 当前专利权人: XILINX, INC.
- 当前专利权人地址: US CA San Jose
- 代理机构: Patterson + Sheridan, LLP
- 主分类号: G06F13/40
- IPC分类号: G06F13/40 ; G06F13/20 ; G06F13/16 ; G06F13/12 ; H03M1/12
摘要:
Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.
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