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    Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture
    1.
    发明授权
    Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture 有权

    公开(公告)号：US10963411B1

    公开(公告)日：2021-03-30

    申请号：US16502141

    申请日：2019-07-03

    申请人： XILINX, INC.

    发明人： Martin L. Voogel ,  Trevor J. Bauer ,  Rafael C. Camarota

    IPC分类号： G06F13/40 ,  G06F13/20 ,  G06F13/16 ,  G06F13/12 ,  H03M1/12

    摘要： Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.

    Regularity of fabrics in programmable logic devices
    2.
    发明授权
    Regularity of fabrics in programmable logic devices 有权

    公开(公告)号：US10726181B1

    公开(公告)日：2020-07-28

    申请号：US16502137

    申请日：2019-07-03

    申请人： XILINX, INC.

    发明人： Martin L. Voogel ,  Trevor J. Bauer ,  Henri Fraisse

    IPC分类号： G06F30/394 ,  G06F30/331 ,  G06F30/392

    摘要： A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.