Invention Grant
- Patent Title: Methods and apparatus to insert buffers in a dataflow graph
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Application No.: US16370934Application Date: 2019-03-30
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Publication No.: US10965536B2Publication Date: 2021-03-30
- Inventor: Kermin E. ChoFleming, Jr. , Jesmin Jahan Tithi , Suresh Srinivasan , Mahesh A. Iyer
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: H04L12/24
- IPC: H04L12/24 ; H04L12/26 ; H04L12/861

Abstract:
Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.
Public/Granted literature
- US20190229996A1 METHODS AND APPARATUS TO INSERT BUFFERS IN A DATAFLOW GRAPH Public/Granted day:2019-07-25
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