Invention Grant
- Patent Title: Methods of forming a channel region of a transistor and methods used in forming a memory array
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Application No.: US16582109Application Date: 2019-09-25
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Publication No.: US10971360B2Publication Date: 2021-04-06
- Inventor: David H. Wells , Anish A. Khandekar , Kunal Shrotri , Jie Li
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L27/115 ; H01L27/11582 ; H01L21/28 ; H01L29/786

Abstract:
A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
Public/Granted literature
- US20200020529A1 Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array Public/Granted day:2020-01-16
Information query
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