LDPC interleaver design for improved error floor performance
Abstract:
Certain aspects of the present disclosure provide techniques and apparatus for low density parity check (LDPC) interleaving with improved error floor performance. A method for wireless communications that may be provided by a transmitting device is provided. The method generally includes encoding one or more information bits using a LDPC code to produce a coded bit sequence comprising systematic bits and parity bits. The transmitting device stores the coded bit sequence in a circular buffer. The transmitting device performs rate matching on the coded bit sequence. The rate matching includes interleaving the parity bits with a partial interleaver and interleaving the systematic bits and interleaved parity bits with a systematic bit priority mapping (SBPM) interleaver. The transmitting device maps the SBPM interleaved bit sequence to constellation points according to a modulation scheme and transmits the modulated bit sequence.
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