Invention Grant
- Patent Title: LDPC interleaver design for improved error floor performance
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Application No.: US16576338Application Date: 2019-09-19
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Publication No.: US10972219B2Publication Date: 2021-04-06
- Inventor: Ying Wang , Jing Jiang , Gabi Sarkis , Joseph Binamira Soriaga , Jing Lei , Seyong Park
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, L.L.P.
- Main IPC: H04L27/36
- IPC: H04L27/36 ; H04L1/00

Abstract:
Certain aspects of the present disclosure provide techniques and apparatus for low density parity check (LDPC) interleaving with improved error floor performance. A method for wireless communications that may be provided by a transmitting device is provided. The method generally includes encoding one or more information bits using a LDPC code to produce a coded bit sequence comprising systematic bits and parity bits. The transmitting device stores the coded bit sequence in a circular buffer. The transmitting device performs rate matching on the coded bit sequence. The rate matching includes interleaving the parity bits with a partial interleaver and interleaving the systematic bits and interleaved parity bits with a systematic bit priority mapping (SBPM) interleaver. The transmitting device maps the SBPM interleaved bit sequence to constellation points according to a modulation scheme and transmits the modulated bit sequence.
Public/Granted literature
- US20200099472A1 LDPC INTERLEAVER DESIGN FOR IMPROVED ERROR FLOOR PERFORMANCE Public/Granted day:2020-03-26
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