Invention Grant
- Patent Title: 3D high-inductive ground plane for crosstalk reduction
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Application No.: US16328535Application Date: 2017-08-29
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Publication No.: US10973116B2Publication Date: 2021-04-06
- Inventor: Jackson Chung Peng Kong , Bok Eng Cheah , Khang Choong Yong , Ramaswamy Parthasarathy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Priority: IN201641033433 20160930
- International Application: PCT/US2017/049222 WO 20170829
- International Announcement: WO2018/063684 WO 20180405
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/03 ; H05K1/11 ; H05K1/18 ; H05K3/00 ; H05K3/10 ; H05K3/46 ; H01P3/00 ; H01P3/08 ; H03H7/38 ; H03H7/42

Abstract:
Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.
Public/Granted literature
- US20190208620A1 3D HIGH-INDUCTIVE GROUND PLANE FOR CROSSTALK REDUCTION Public/Granted day:2019-07-04
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