Invention Grant
- Patent Title: Architected state retention for a frequent operating state switching processor
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Application No.: US15496290Application Date: 2017-04-25
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Publication No.: US10990159B2Publication Date: 2021-04-27
- Inventor: Bernard Joseph Semeria , John H. Mylius , Pradeep Kanapathipillai , Richard F. Russo , Shih-Chieh Wen , Richard H. Larson
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Kowert Hood Munyon Rankin and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F3/06 ; G06F1/3287 ; G06F1/3228 ; G06F1/3206 ; G06F1/3296

Abstract:
Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.
Public/Granted literature
- US20180307297A1 ARCHITECTED STATE RETENTION Public/Granted day:2018-10-25
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