公开(公告)号：US20210064539A1

公开(公告)日：2021-03-04

申请号：US16874997

申请日：2020-05-15

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard Joseph Semeria ,  Michael J. Swift ,  Pradeep Kanapathipillai ,  David J. Williamson

IPC: G06F12/1009 ,  G06F12/1072 ,  G06F12/0873 ,  G06F12/14

Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

公开(公告)号：US08762755B2

公开(公告)日：2014-06-24

申请号：US13921100

申请日：2013-06-18

Applicant: Apple Inc.

Inventor： Joshua de Cesare ,  Bernard Joseph Semeria ,  Michael Smith

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/14

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

Abstract: Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.

Abstract translation: 描述用于管理数据处理系统中的功耗的方法和系统。 在一个实施例中，数据处理系统包括通用处理单元，图形处理单元（GPU），至少一个外围设备接口控制器，耦合到通用处理单元的至少一个总线，以及耦合到至少 通用处理单元和GPU。 功率控制器被配置为响应于通用处理单元的指令队列的第一状态而为通用处理单元断电，并且被配置为响应于指令的第二状态而关闭GPU的电源 排队GPU 第一状态和第二状态表示具有对于将来的事件或动作的指令或指令的指令队列。

公开(公告)号：US20180307297A1

公开(公告)日：2018-10-25

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F1/32 ,  G06F9/38 ,  G06F3/06

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3296 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/067 ,  G06F9/3802

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

公开(公告)号：US09632563B2

公开(公告)日：2017-04-25

申请号：US14159705

申请日：2014-01-21

Applicant: Apple Inc.

Inventor： Joshua P. de Cesare ,  Bernard Joseph Semeria ,  Michael John Smith

IPC: G06F13/36 ,  G06F1/32 ,  G06F9/48 ,  G06F13/24

CPC classification number: G06F1/3287 ,  G06F9/4825 ,  G06F13/24 ,  G06F13/36 ,  Y02D10/14 ,  Y02D10/24

Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

公开(公告)号：US11221962B2

公开(公告)日：2022-01-11

申请号：US16874997

申请日：2020-05-15

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard Joseph Semeria ,  Michael J. Swift ,  Pradeep Kanapathipillai ,  David J. Williamson

IPC: G06F12/1009 ,  G06F12/14 ,  G06F12/0873 ,  G06F12/1072

Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

公开(公告)号：US10990159B2

公开(公告)日：2021-04-27

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F9/38 ,  G06F3/06 ,  G06F1/3287 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

公开(公告)号：US20140164661A1

公开(公告)日：2014-06-12

申请号：US14159705

申请日：2014-01-21

Applicant: Apple Inc.

Inventor： Joshua P. de Cesare ,  Bernard Joseph Semeria ,  Michael John Smith

IPC: G06F1/32 ,  G06F13/24

CPC classification number: G06F1/3287 ,  G06F9/4825 ,  G06F13/24 ,  G06F13/36 ,  Y02D10/14 ,  Y02D10/24

Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

Abstract translation: 具有中断的数据处理系统和用于操作这种数据处理系统的方法和用于引起这种方法并包含可执行程序指令的机器可读介质。 在一个实施例中，示例性数据处理系统包括处理系统，耦合到处理系统的中断控制器和耦合到中断控制器的定时器电路。 中断控制器被配置为向处理系统提供第一中断信号和第二中断信号。 处理系统被配置为维持多个进程的时间相关事件的数据结构（例如，列表），并且处理系统被配置为对代表一段时间的值的输入进行加密， 进入定时器电路。 定时器电路被配置为响应于该时间段的到期而导致第一中断信号的断言。

公开(公告)号：US20130283076A1

公开(公告)日：2013-10-24

申请号：US13921100

申请日：2013-06-18

Applicant: Apple Inc.

Inventor： Joshua De Cesare ,  Bernard Joseph Semeria ,  Michael Smith

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

Abstract: Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.

Abstract translation: 描述用于管理数据处理系统中的功耗的方法和系统。 在一个实施例中，数据处理系统包括通用处理单元，图形处理单元（GPU），至少一个外围设备接口控制器，耦合到通用处理单元的至少一个总线，以及耦合到至少 通用处理单元和GPU。 功率控制器被配置为响应于通用处理单元的指令队列的第一状态而为通用处理单元断电，并且被配置为响应于指令的第二状态而关闭GPU的电源 排队GPU 第一状态和第二状态表示具有对于将来的事件或动作的指令或指令的指令队列。