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公开(公告)号：US20240311319A1
公开(公告)日：2024-09-19
申请号：US18674203
申请日：2024-05-24
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20180307297A1
公开(公告)日：2018-10-25
申请号：US15496290
申请日：2017-04-25
Applicant: Apple Inc.
Inventor： Bernard Joseph Semeria , John H. Mylius , Pradeep Kanapathipillai , Richard F. Russo , Shih-Chieh Wen , Richard H. Larson
CPC classification number: G06F1/3287 , G06F1/3206 , G06F1/3228 , G06F1/3296 , G06F3/0619 , G06F3/0625 , G06F3/065 , G06F3/067 , G06F9/3802
Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.
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公开(公告)号：US10416692B2
公开(公告)日：2019-09-17
申请号：US15708229
申请日：2017-09-19
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Ramesh B. Gunna , Shih-Chieh Wen
IPC: G05F1/10 , G05F1/46 , H03K5/04 , H03K19/003 , G06F1/26
Abstract: A method and apparatus for reducing capacitor noise in electronic systems is disclosed. A system includes at least one functional circuit block coupled to receive a variable supply voltage. The value of the supply voltage is controlled by a power management circuit. Changing a performance state of the functional circuit block includes increasing the supply voltage for higher performance, and reducing the supply voltage for reduced performance demands. The power management circuit, in changing to a higher performance state, increases the supply voltage at a first rate. A rate control circuit causes the power management circuit to reduce the supply voltage, when changing to a lower performance state, at a second rate that is less than the first rate.
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公开(公告)号：US10223123B1
公开(公告)日：2019-03-05
申请号：US15133804
申请日：2016-04-20
Applicant: Apple Inc.
Inventor： Conrado Blasco , Brett S. Feero , David Williamson , Ian D. Kountanis , Shih-Chieh Wen
IPC: G06F1/32 , G06F9/30 , G06F9/38 , G06F12/0875 , G06F1/3287 , G06F1/3234
Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.
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公开(公告)号：US11698671B2
公开(公告)日：2023-07-11
申请号：US17481703
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Preethi Bhargavi Sama , Richard H. Larson , Shih-Chieh Wen , Srikanth Balasubramanian
IPC: G06F1/32 , G06F1/3234
CPC classification number: G06F1/3234
Abstract: Some aspects of this disclosure relate to a peak power manager that includes a first power estimate accumulator circuit configured to receive one or more power estimates associated with one or more subsystems and to generate a first accumulated power estimate. The peak power manage can further include a first-in first-out (FIFO) storage circuit configured to store a plurality of first accumulated power estimates associated with a plurality of clock cycles corresponding to a moving time interval window. The peak power manager can further include a second power estimate accumulator circuit configured to accumulate the plurality of first accumulated power estimates to generate a second accumulated power estimate and a control circuit. The control circuit can be configured to compare the second accumulated power estimate with a threshold power and generate a control signal to control one or more events at the one or more subsystems in response to the second accumulated power estimate satisfying a condition associated with the threshold power.
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Patent Agency Ranking
公开(公告)号：US20220083484A1
公开(公告)日：2022-03-17
申请号：US17246311
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US10147464B1
公开(公告)日：2018-12-04
申请号：US15628017
申请日：2017-06-20
Applicant: Apple Inc.
Inventor： Shih-Chieh Wen , Jong-Suk Lee , Ramesh B. Gunna
IPC: G06F12/08 , G11C5/14 , G06F1/26 , G06F9/28 , G06F1/30 , G06F11/20 , G06F11/30 , G06F1/00 , G06F9/00
Abstract: An IC in which a power state of a circuit in one power domain is managed based at least in part on a power state of a circuit in another power domain is disclosed. In one embodiment, an IC includes first and second functional circuit blocks in first and second power domains, respectively. A third functional block shared by the first and second is also implemented in the first power domain. A power management unit may control power states of each of the first, second, and third functional circuit blocks. The power management circuit may, when the first functional circuit block is in a sleep state, set a power state of the third functional block in accordance with that of the second functional circuit block.
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公开(公告)号：US12007920B2
公开(公告)日：2024-06-11
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20230251985A1
公开(公告)日：2023-08-10
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11630789B2
公开(公告)日：2023-04-18
申请号：US17246311
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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