Invention Grant
- Patent Title: Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification
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Application No.: US15622248Application Date: 2017-06-14
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Publication No.: US10997339B2Publication Date: 2021-05-04
- Inventor: John Stuart Freeman , Byron Sinclair , Dirk Seynhaeve
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F30/3323
- IPC: G06F30/3323 ; G06F30/33
Abstract:
A method for designing a system on a target device includes performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system. Verification is performed on the system that examines a parallel nature of the system by using the serial testbench.
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