Described herein are ferroelectric memory cells and corresponding methods and devices. For example, in some embodiments, a ferroelectric memory cell disclosed herein includes one access transistor and one ferroelectric transistor (1T-1FE-FET cell). The access transistor is coupled to the ferroelectric transistor by sharing its source/drain terminal with that of the ferroelectric transistor and is used for both READ and WRITE access to the ferroelectric transistor.