Invention Grant
- Patent Title: Methods, apparatus and system for a self-aligned gate cut on a semiconductor device
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Application No.: US16730712Application Date: 2019-12-30
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Publication No.: US10998422B2Publication Date: 2021-05-04
- Inventor: Hui Zang , Laertis Economikos , Ruilong Xie
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L29/66 ; H01L27/02 ; H01L21/8238
Abstract:
At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
Public/Granted literature
- US20200185509A1 METHODS, APPARATUS AND SYSTEM FOR A SELF-ALIGNED GATE CUT ON A SEMICONDUCTOR DEVICE Public/Granted day:2020-06-11
Information query
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