Invention Grant
- Patent Title: Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
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Application No.: US16881549Application Date: 2020-05-22
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Publication No.: US10998423B2Publication Date: 2021-05-04
- Inventor: Van H. Le , Scott B. Clendenning , Martin M. Mitan , Szuya S. Liao
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; B82Y10/00 ; H01L21/02 ; H01L29/06 ; H01L29/423 ; H01L29/775 ; H01L29/78 ; H01L29/786 ; H01L21/762
Abstract:
Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
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