公开(公告)号：US11532724B2

公开(公告)日：2022-12-20

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10720508B2

公开(公告)日：2020-07-21

申请号：US15750158

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Van H. Le ,  Scott B. Clendenning ,  Martin M. Mitan ,  Szuya S. Liao

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/762

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

公开(公告)号：US20210143265A1

公开(公告)日：2021-05-13

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10998423B2

公开(公告)日：2021-05-04

申请号：US16881549

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Scott B. Clendenning ,  Martin M. Mitan ,  Szuya S. Liao

IPC: H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/762

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

公开(公告)号：US11869889B2

公开(公告)日：2024-01-09

申请号：US16579055

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. Clendenning ,  Jessica Torres ,  Lukas Baumgartel ,  Kiran Chikkadi ,  Diane Lancaster ,  Matthew V. Metz ,  Florian Gstrein ,  Martin M. Mitan ,  Rami Hourani

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20200020786A1

公开(公告)日：2020-01-16

申请号：US16517220

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/265 ,  H01L29/51 ,  H01L29/775

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US11810980B2

公开(公告)日：2023-11-07

申请号：US16457621

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Pei-Hua Wang ,  Bernhard Sell ,  Martin M. Mitan ,  Leonard C. Pipes

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/768 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/78696 ,  H01L21/76829 ,  H01L27/0688 ,  H01L27/1259 ,  H01L29/6675 ,  H01L29/78618

Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

公开(公告)号：US10971600B2

公开(公告)日：2021-04-06

申请号：US16517220

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10396176B2

公开(公告)日：2019-08-27

申请号：US15506101

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L29/49 ,  H01L21/265 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.