Invention Grant
- Patent Title: Stopping criteria for layered iterative error correction
-
Application No.: US16244627Application Date: 2019-01-10
-
Publication No.: US10998923B2Publication Date: 2021-05-04
- Inventor: Mustafa N. Kaynak , William H. Radke , Patrick R. Khayat , Sivagnanam Parthasarathy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/37 ; G06F11/10 ; G11C29/52 ; H03M13/29 ; H03M13/15

Abstract:
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.
Public/Granted literature
- US20190149175A1 STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION Public/Granted day:2019-05-16
Information query
IPC分类: