Invention Grant
- Patent Title: Master set of read voltages for a non-volatile memory (NVM) to mitigate cross-temperature effects
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Application No.: US16547925Application Date: 2019-08-22
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Publication No.: US11017850B2Publication Date: 2021-05-25
- Inventor: Kurt Walter Getreuer , Darshana H. Mehta , Antoine Khoueir , Christopher Joseph Curl
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Hall Estill Attorneys at Law
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C11/56 ; G11C16/26 ; G11C16/34 ; H03M13/11 ; G06F11/07

Abstract:
Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.
Public/Granted literature
- US20210057024A1 MASTER SET OF READ VOLTAGES FOR A NON-VOLATILE MEMORY (NVM) TO MITIGATE CROSS-TEMPERATURE EFFECTS Public/Granted day:2021-02-25
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