公开(公告)号：US20210133025A1

公开(公告)日：2021-05-06

申请号：US16670329

申请日：2019-10-31

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Ara Patapoutian ,  Colin Hill ,  Kurt Walter Getreuer ,  Darshana H. Mehta

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  H03M13/11

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

公开(公告)号：US11017850B2

公开(公告)日：2021-05-25

申请号：US16547925

申请日：2019-08-22

Applicant: Seagate Technology LLC

Inventor： Kurt Walter Getreuer ,  Darshana H. Mehta ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H03M13/11 ,  G06F11/07

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.

公开(公告)号：US20210057024A1

公开(公告)日：2021-02-25

申请号：US16547925

申请日：2019-08-22

Applicant: Seagate Technology LLC

Inventor： Kurt Walter Getreuer ,  Darshana H. Mehta ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G06F11/07 ,  H03M13/11

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.

公开(公告)号：US11086717B2

公开(公告)日：2021-08-10

申请号：US16670329

申请日：2019-10-31

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Ara Patapoutian ,  Colin Hill ,  Kurt Walter Getreuer ,  Darshana H. Mehta

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  H03M13/11 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

公开(公告)号：US11017864B2

公开(公告)日：2021-05-25

申请号：US16453211

申请日：2019-06-26

Applicant: Seagate Technology LLC

Inventor： Kurt Walter Getreuer ,  Darshana H. Mehta ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G01K1/14

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.

公开(公告)号：US10956064B2

公开(公告)日：2021-03-23

申请号：US16456809

申请日：2019-06-28

Applicant: Seagate Technology LLC

Inventor： Darshana H. Mehta ,  Kurt Walter Getreuer ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.