- 专利标题: Semiconductor device package with stress buffering layer and method for manufacturing the same
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申请号: US16434075申请日: 2019-06-06
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公开(公告)号: US11018120B2公开(公告)日: 2021-05-25
- 发明人: Chien-Mei Huang , Shih-Yu Wang , I-Ting Lin , Wen Hung Huang , Yuh-Shan Su , Chih-Cheng Lee , Hsing Kuo Tien
- 申请人: Advanced Semiconductor Engineering, Inc.
- 申请人地址: TW Kaohsiung
- 专利权人: Advanced Semiconductor Engineering, Inc.
- 当前专利权人: Advanced Semiconductor Engineering, Inc.
- 当前专利权人地址: TW Kaohsiung
- 代理机构: Foley & Lardner LLP
- 主分类号: H01L25/16
- IPC分类号: H01L25/16 ; H01L23/31 ; H01L23/00 ; H01L23/522 ; H01L21/56 ; H01L23/528 ; H01L23/29
摘要:
A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
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