公开(公告)号：US11432406B2

公开(公告)日：2022-08-30

申请号：US17025939

申请日：2020-09-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wu Chou Hsu ,  Hsing Kuo Tien ,  Chih-Cheng Lee ,  Min-Yao Chen

IPC: H02K5/04 ,  H02K33/00 ,  H05K3/30 ,  H01L21/00 ,  H01L21/56 ,  H01L23/10 ,  H01L23/498 ,  H01L23/544 ,  H05K1/18 ,  H05K1/02 ,  H01L21/48

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

公开(公告)号：US11335650B2

公开(公告)日：2022-05-17

申请号：US16899515

申请日：2020-06-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wu Chou Hsu ,  Chih-Cheng Lee ,  Min-Yao Chen ,  Hsing Kuo Tien

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.

公开(公告)号：US10276507B2

公开(公告)日：2019-04-30

申请号：US15635128

申请日：2017-06-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L23/552 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L21/683 ,  H01L23/13 ,  H01L25/16 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.

公开(公告)号：US11830834B2

公开(公告)日：2023-11-28

申请号：US17372339

申请日：2021-07-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo Tien ,  Chih-Cheng Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/24 ,  H01L25/162 ,  H01L2224/05565 ,  H01L2224/05573 ,  H01L2224/24225

Abstract: A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.

公开(公告)号：US09997442B1

公开(公告)日：2018-06-12

申请号：US15379362

申请日：2016-12-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chai-Chi Lin ,  Chih-Cheng Lee ,  Hsing Kuo Tien ,  Chih-Yung Yang

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L25/18 ,  H01L25/16 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225

Abstract: A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.

公开(公告)号：US09721899B2

公开(公告)日：2017-08-01

申请号：US14732529

申请日：2015-06-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L23/36 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/36 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/215 ,  H01L2224/24145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.

公开(公告)号：US11721678B2

公开(公告)日：2023-08-08

申请号：US17330240

申请日：2021-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/17 ,  H01L23/293 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US11715694B2

公开(公告)日：2023-08-01

申请号：US17373532

申请日：2021-07-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo Tien ,  Chih Cheng Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5384

Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US11469186B2

公开(公告)日：2022-10-11

申请号：US16938818

申请日：2020-07-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo Tien ,  Chih-Cheng Lee

IPC: H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.

公开(公告)号：US09887167B1

公开(公告)日：2018-02-06

申请号：US15269787

申请日：2016-09-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee ,  Hsing Kuo Tien ,  Li Chuan Tsai

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/29191 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A package structure includes a carrier defining a cavity in which a die is disposed. A dielectric material fills the cavity around the die. A first conductive layer is disposed over a first surface of the carrier. A first dielectric layer is disposed over an active surface of the die, the first conductive layer and the first surface of the carrier. A first conductive pattern is disposed over the first dielectric layer, and is electrically connected to the first conductive layer and to the active surface of the die. A second dielectric layer is disposed over the second surface of the carrier and defines a hole having a wall aligned with a sidewall of the cavity. A second conductive layer is disposed over the second dielectric layer. A third conductive layer is disposed on the sidewall of the cavity and the wall of the second dielectric layer.