公开(公告)号：US11018120B2

公开(公告)日：2021-05-25

申请号：US16434075

申请日：2019-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US10134677B1

公开(公告)日：2018-11-20

申请号：US15596956

申请日：2017-05-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Shih-Yu Wang ,  Chang Chi Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2221/68359

Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

公开(公告)号：US11791227B2

公开(公告)日：2023-10-17

申请号：US17317770

申请日：2021-05-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuoching Cheng ,  Yuan-Feng Chiang ,  Ya Fang Chan ,  Wen-Long Lu ,  Shih-Yu Wang

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/16

CPC classification number: H01L23/31 ,  H01L21/56 ,  H01L23/16 ,  H01L23/5386 ,  H01L25/0655

Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.

公开(公告)号：US11721678B2

公开(公告)日：2023-08-08

申请号：US17330240

申请日：2021-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/17 ,  H01L23/293 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.