- 专利标题： System, method and computer program product for automatic generation of sizing constraints by reusing existing electronic designs
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申请号： US16523416申请日： 2019-07-26
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公开(公告)号： US11048852B1公开(公告)日： 2021-06-29
- 发明人: Elias Lee Fallon , Wangyang Zhang , Sheng Qian
- 申请人： Cadence Design Systems, Inc.
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Holland & Knight LLP
- 代理商 Mark H. Whittenberger, Esq.
- 主分类号： G06F30/30
- IPC分类号： G06F30/30 ; G06F30/398 ; G06N20/00 ; G06F30/20 ; G06F30/27 ; G06F30/373 ; G06F30/337
摘要：
The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.
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