公开(公告)号：US11048852B1

公开(公告)日：2021-06-29

申请号：US16523416

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  Wangyang Zhang ,  Sheng Qian

IPC: G06F30/30 ,  G06F30/398 ,  G06N20/00 ,  G06F30/20 ,  G06F30/27 ,  G06F30/373 ,  G06F30/337

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.

公开(公告)号：US11087060B1

公开(公告)日：2021-08-10

申请号：US16524859

申请日：2019-07-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane ,  Sheng Qian

IPC: G06F30/39 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.

公开(公告)号：US10997351B1

公开(公告)日：2021-05-04

申请号：US16992205

申请日：2020-08-13

Applicant: Cadence Design Systems, Inc.

Inventor： Sheng Qian ,  Sai Bhushan ,  Monica Goel

IPC: G06F30/392 ,  G06F30/3308

Abstract: Embodiments included herein are directed towards method for electronic design. Embodiments may include receiving, using at least one processor, a placed layout and one or more electronic design simulation datasets including current information associated with at least one pin. Embodiments may further include estimating a width to support the current information associated with the at least one pin and updating a pin size associated with the at least one pin based upon, at least in part, the estimated width. Embodiments may also include identifying at least one pin that is above a predetermined threshold and splitting the at least one pin that is above the predetermined threshold into a plurality of pins. Embodiments may further include generating one or more width-spacing-pattern tracks for one or more internal nets based upon, at least in part, the updated pin size.

公开(公告)号：US11275881B1

公开(公告)日：2022-03-15

申请号：US17140510

申请日：2021-01-04

Applicant: Cadence Design Systems, Inc.

Inventor： Weifu Li ,  Elias Lee Fallon ,  Supriya Ananthram ,  Weiyi Qi ,  Sheng Qian

IPC: G06F30/3947 ,  G06F30/398 ,  G06F30/31 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.

公开(公告)号：US11003825B1

公开(公告)日：2021-05-11

申请号：US16583643

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Saleha Khatun ,  Sheng Qian ,  Wangyang Zhang ,  Elias Lee Fallon

IPC: G06F30/30 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.