公开(公告)号：US11087060B1

公开(公告)日：2021-08-10

申请号：US16524859

申请日：2019-07-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane ,  Sheng Qian

IPC: G06F30/39 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.

公开(公告)号：US11562110B1

公开(公告)日：2023-01-24

申请号：US16587394

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Hua Luo ,  Elias Lee Fallon

IPC: G06F17/00 ,  G06F30/20 ,  G06N20/00 ,  G06N7/00

Abstract: A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.

公开(公告)号：US12045730B1

公开(公告)日：2024-07-23

申请号：US16238274

申请日：2019-01-02

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  David Allan White ,  Regis R Colwell ,  Hongzhou Liu ,  Hui Xu ,  Wangyang Zhang ,  Shang Li ,  Hua Luo

IPC: G06N3/126 ,  G06F30/392

CPC classification number: G06N3/126 ,  G06F30/392

Abstract: The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

公开(公告)号：US11275882B1

公开(公告)日：2022-03-15

申请号：US16523112

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane

IPC: G06F30/398 ,  G06K9/62 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should be grouped together.

公开(公告)号：US11620548B1

公开(公告)日：2023-04-04

申请号：US16898702

申请日：2020-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： Sai Bhushan ,  Elias Lee Fallon ,  Chirag Ahuja

IPC: G06F30/3308 ,  G06F30/27 ,  G06N5/04 ,  G06N5/00 ,  G06N20/20

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.

公开(公告)号：US11544574B1

公开(公告)日：2023-01-03

申请号：US16522035

申请日：2019-07-25

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon

IPC: G06N5/00 ,  G06N20/00 ,  G06F30/398

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.

公开(公告)号：US11048852B1

公开(公告)日：2021-06-29

申请号：US16523416

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  Wangyang Zhang ,  Sheng Qian

IPC: G06F30/30 ,  G06F30/398 ,  G06N20/00 ,  G06F30/20 ,  G06F30/27 ,  G06F30/373 ,  G06F30/337

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.

公开(公告)号：US11275881B1

公开(公告)日：2022-03-15

申请号：US17140510

申请日：2021-01-04

Applicant: Cadence Design Systems, Inc.

Inventor： Weifu Li ,  Elias Lee Fallon ,  Supriya Ananthram ,  Weiyi Qi ,  Sheng Qian

IPC: G06F30/3947 ,  G06F30/398 ,  G06F30/31 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.

公开(公告)号：US11003825B1

公开(公告)日：2021-05-11

申请号：US16583643

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Saleha Khatun ,  Sheng Qian ,  Wangyang Zhang ,  Elias Lee Fallon

IPC: G06F30/30 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.