公开(公告)号：US12045730B1

公开(公告)日：2024-07-23

申请号：US16238274

申请日：2019-01-02

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  David Allan White ,  Regis R Colwell ,  Hongzhou Liu ,  Hui Xu ,  Wangyang Zhang ,  Shang Li ,  Hua Luo

IPC: G06N3/126 ,  G06F30/392

CPC classification number: G06N3/126 ,  G06F30/392

Abstract: The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

公开(公告)号：US11275882B1

公开(公告)日：2022-03-15

申请号：US16523112

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane

IPC: G06F30/398 ,  G06K9/62 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should be grouped together.

公开(公告)号：US11003825B1

公开(公告)日：2021-05-11

申请号：US16583643

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Saleha Khatun ,  Sheng Qian ,  Wangyang Zhang ,  Elias Lee Fallon

IPC: G06F30/30 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.

公开(公告)号：US10325056B1

公开(公告)日：2019-06-18

申请号：US15179087

申请日：2016-06-10

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu

IPC: G06F17/50

Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

公开(公告)号：US10275555B1

公开(公告)日：2019-04-30

申请号：US15280839

申请日：2016-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Shikha Sharma ,  Hongzhou Liu

IPC: G06F9/455 ,  G06F17/50

Abstract: Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further includes calculating the first hyper-parameter and the second hyper-parameter using a cross-validation, obtaining the first post-layout parameter and the second post-layout parameter based on the first hyper-parameter and the second hyper-parameter and estimating the yield of the circuit design using a non-normal distribution parameterized by the obtained first post-layout parameter and second post-layout parameter.

公开(公告)号：US09836564B1

公开(公告)日：2017-12-05

申请号：US14683021

申请日：2015-04-09

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.

公开(公告)号：US11544574B1

公开(公告)日：2023-01-03

申请号：US16522035

申请日：2019-07-25

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon

IPC: G06N5/00 ,  G06N20/00 ,  G06F30/398

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.

公开(公告)号：US11048852B1

公开(公告)日：2021-06-29

申请号：US16523416

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  Wangyang Zhang ,  Sheng Qian

IPC: G06F30/30 ,  G06F30/398 ,  G06N20/00 ,  G06F30/20 ,  G06F30/27 ,  G06F30/373 ,  G06F30/337

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.

公开(公告)号：US09805158B1

公开(公告)日：2017-10-31

申请号：US14942956

申请日：2015-11-16

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Stephan Weber ,  Wangyang Zhang

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009

Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations. A potential twenty-fold reduction in overall design specification verification time may be achieved.

公开(公告)号：US11562110B1

公开(公告)日：2023-01-24

申请号：US16587394

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Hua Luo ,  Elias Lee Fallon

IPC: G06F17/00 ,  G06F30/20 ,  G06N20/00 ,  G06N7/00

Abstract: A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.