发明授权
- 专利标题： Techniques for forming vias and other interconnects for integrated circuit structures
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申请号： US16647691申请日： 2017-11-03
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公开(公告)号： US11069609B2公开(公告)日： 2021-07-20
- 发明人: Sasikanth Manipatruni , Jasmeet S. Chawla , Chia-Ching Lin , Dmitri E. Nikonov , Ian A. Young , Robert L. Bristol
- 申请人： INTEL CORPORATION
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt P.C.
- 国际申请： PCT/US2017/059980 WO 20171103
- 国际公布： WO2019/089045 WO 20190509
- 主分类号： H01L23/522
- IPC分类号： H01L23/522 ; H01F10/32 ; H01L21/768 ; H01L23/528 ; H01L27/22 ; H01L43/02
摘要：
Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.
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