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公开(公告)号：US11990899B2
公开(公告)日：2024-05-21
申请号：US17152552
申请日：2021-01-19
申请人： Intel Corporation
发明人： Sasikanth Manipatruni , Ian A. Young , Dmitri E. Nikonov , Uygar E. Avci , Patrick Morrow , Anurag Chaudhry
CPC分类号： H03K19/0002 , H03K19/18 , H10N50/85 , H10N52/00 , H10N52/80
摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.
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公开(公告)号：US20230187407A1
公开(公告)日：2023-06-15
申请号：US17548304
申请日：2021-12-10
申请人： Intel Corporation
发明人： Carleton L. Molnar , Adel A. Elsherbini , Tanay Karnik , Shawna M. Liff , Robert J. Munoz , Julien Sebot , Johanna M. Swan , Nevine Nassif , Gerald S. Pasdast , Krishna Bharath , Neelam Chandwani , Dmitri E. Nikonov
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00
CPC分类号： H01L25/0652 , H01L23/481 , H01L24/08 , H01L24/20 , H01L2224/2101 , H01L2224/08147 , H01L2924/37001 , H01L2924/1427
摘要： A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.
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公开(公告)号：US20210143819A1
公开(公告)日：2021-05-13
申请号：US17152552
申请日：2021-01-19
申请人： Intel Corporation
发明人： Sasikanth Manipatruni , Ian A. Young , Dmitri E. Nikonov , Uygar E. Avci , Patrick Morrow , Anurag Chaudhry
摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.
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公开(公告)号：US10944399B2
公开(公告)日：2021-03-09
申请号：US15779074
申请日：2016-12-23
申请人： Intel Corporation
发明人： Sasikanth Manipatruni , Ian A. Young , Dmitri E. Nikonov , Uygar E. Avci , Patrick Morrow , Anurag Chaudhry
摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.
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公开(公告)号：US10910556B2
公开(公告)日：2021-02-02
申请号：US16081001
申请日：2016-03-29
申请人： Intel Corporation
摘要： Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.
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公开(公告)号：US20200321393A1
公开(公告)日：2020-10-08
申请号：US16305370
申请日：2016-06-28
申请人： Intel Corporation
摘要： A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.
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公开(公告)号：US20190312086A1
公开(公告)日：2019-10-10
申请号：US16347792
申请日：2016-12-05
申请人： Intel Corporation
摘要： An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material.
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公开(公告)号：US10347830B2
公开(公告)日：2019-07-09
申请号：US16046189
申请日：2018-07-26
申请人： Intel Corporation
IPC分类号： H01L45/00 , G06F12/02 , G11C14/00 , G11C11/16 , G11C8/16 , G11C11/00 , G11C13/00 , H01L27/02 , H01L27/24
摘要： Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.
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公开(公告)号：US20190198754A1
公开(公告)日：2019-06-27
申请号：US16329721
申请日：2016-09-30
申请人： Intel Corporation
IPC分类号： H01L43/10 , H01L27/22 , H01L41/187 , H01L41/193 , H01L41/20 , G11C11/16 , H01F10/32 , H01L43/02
CPC分类号： H01L43/10 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01F10/123 , H01F10/126 , H01F10/3254 , H01L27/228 , H01L41/00 , H01L41/1871 , H01L41/1875 , H01L41/1876 , H01L41/1878 , H01L41/193 , H01L41/20 , H01L43/02 , H01L43/08
摘要： An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.
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公开(公告)号：US10263036B2
公开(公告)日：2019-04-16
申请号：US15508430
申请日：2014-09-25
申请人： Intel Corporation
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Asif Khan , Raseong Kim , Tahir Ghani , Ian A. Young
IPC分类号： H01L29/82 , H01L27/22 , G11C11/16 , H01L43/02 , H01L43/08 , H01L27/20 , H01L41/20 , H01L43/10 , H01L27/11507 , H01L27/11502 , H01L49/02
摘要： Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.
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