Invention Grant
- Patent Title: Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors
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Application No.: US16641032Application Date: 2017-09-29
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Publication No.: US11101356B2Publication Date: 2021-08-24
- Inventor: Glenn A. Glass , Anand S. Murthy , Karthik Jambunathan , Cory C. Bomberger , Tahir Ghani , Jack T. Kavalieros , Benjamin Chu-Kung , Seung Hoon Sung , Siddharth Chouksey
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/054293 WO 20170929
- International Announcement: WO2019/066896 WO 20190404
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/16 ; H01L29/417 ; H01L29/423 ; H01L29/78 ; H01L29/786

Abstract:
Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.
Public/Granted literature
- US20210005722A1 DOPED INSULATOR CAP TO REDUCE SOURCE/DRAIN DIFFUSION FOR GERMANIUM NMOS TRANSISTORS Public/Granted day:2021-01-07
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