- 专利标题： Asymmetric high-k dielectric for reducing gate induced drain leakage
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申请号： US16983764申请日： 2020-08-03
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公开(公告)号： US11101357B2公开(公告)日： 2021-08-24
- 发明人: Anthony I. Chou , Arvind Kumar , Chung-Hsun Lin , Shreesh Narasimha , Claude Ortolland , Jonathan T. Shaw
- 申请人： Tessera, Inc.
- 申请人地址： US CA San Jose
- 专利权人： Tessera, Inc.
- 当前专利权人： Tessera, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Lee & Hayes, P.C.
- 主分类号： H01L29/423
- IPC分类号： H01L29/423 ; H01L29/51 ; H01L21/265 ; H01L29/66 ; H01L21/28 ; H01L21/02 ; H01L21/426 ; H01L21/8234 ; H01L21/3115 ; H01L21/324 ; H01L21/84 ; H01L29/40 ; H01L29/78 ; H01L21/283 ; H01L21/308 ; H01L29/417
摘要：
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
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