Invention Grant
- Patent Title: Hardware coherence for memory controller
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Application No.: US16882216Application Date: 2020-05-22
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Publication No.: US11106584B2Publication Date: 2021-08-31
- Inventor: Abhijeet Ashok Chachad , David Matthew Thompson , Naveen Bhoria
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Charles A. Brill; Frank D. Cimino
- Main IPC: G06F12/0811
- IPC: G06F12/0811 ; G06F12/0815 ; G06F12/128 ; G06F12/0817 ; G06F12/084 ; G06F9/30 ; G06F11/30 ; G06F12/0808 ; G06F13/16 ; G06F9/38 ; G06F9/46 ; G06F9/54 ; G06F12/0895

Abstract:
A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.
Public/Granted literature
- US20200371930A1 HARDWARE COHERENCE FOR MEMORY CONTROLLER Public/Granted day:2020-11-26
Information query
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