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    PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
    3.
    发明公开
    PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE 审中-公开

    公开(公告)号：US20230251975A1

    公开(公告)日：2023-08-10

    申请号：US18194708

    申请日：2023-04-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

    IPC: G06F12/1045 ,  G06F15/78

    CPC classification number: G06F12/1045 ,  G06F15/7807 ,  G06F2212/50 ,  G06F2212/301

    Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

    MULTI-LEVEL CACHE SECURITY
    8.
    发明申请
    MULTI-LEVEL CACHE SECURITY 审中-公开

    公开(公告)号：US20200371927A1

    公开(公告)日：2020-11-26

    申请号：US16882380

    申请日：2020-05-22

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

    IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/1081 ,  G06F21/79 ,  G06F9/46

    Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.

    WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
    9.
    发明申请
    WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY 审中-公开

    公开(公告)号：US20200371918A1

    公开(公告)日：2020-11-26

    申请号：US16874516

    申请日：2020-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

    IPC: G06F12/0811 ,  G06F12/0815 ,  G06F3/06 ,  G06F9/38 ,  G06F12/126

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

    PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
    10.
    发明申请
    PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM 审中-公开

    公开(公告)号：US20200320006A1

    公开(公告)日：2020-10-08

    申请号：US16856169

    申请日：2020-04-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung ONG

    IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/0811

    Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

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