Invention Grant
- Patent Title: System, apparatus and method for dynamic priority-aware compression for interconnect fabrics
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Application No.: US16445556Application Date: 2019-06-19
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Publication No.: US11108406B2Publication Date: 2021-08-31
- Inventor: Simon N. Peffers , Vinodh Gopal , Kirk Yap
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop Pruer & Hu, P.C.
- Main IPC: H03M7/38
- IPC: H03M7/38 ; H03M7/30 ; G06F12/0875 ; G06F12/0888 ; G06F9/54
Abstract:
In one embodiment, an apparatus includes: a compression circuit to compress data blocks of one or more traffic classes; and a control circuit coupled to the compression circuit, where the control circuit is to enable the compression circuit to concurrently compress data blocks of a first traffic class and not to compress data blocks of a second traffic class. Other embodiments are described and claimed.
Public/Granted literature
- US20190305797A1 System, Apparatus And Method For Dynamic Priority-Aware Compression For Interconnect Fabrics Public/Granted day:2019-10-03
Information query
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