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公开(公告)号：US20200052494A1
公开(公告)日：2020-02-13
申请号：US16057588
申请日：2018-08-07
Applicant: Intel Corporation
Inventor： Naoki Matsumura , Simon N. Peffers , Steven Lloyd , Michael T. Crocker , Aaron Gorius
IPC: H02J7/00
Abstract: In some examples, a control unit is configured to adjust charge termination voltage of a rechargeable energy storage device. The control unit is adapted to charge the rechargeable energy storage device to a charge termination voltage where the rechargeable energy storage device has capacity to support peak load but comes close to a system shutdown voltage after supporting peak load. The control unit is also adapted to increase the charge termination voltage if a voltage of the rechargeable energy storage device is near a system shutdown voltage after supporting peak load.
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公开(公告)号：US20190188132A1
公开(公告)日：2019-06-20
申请号：US15845271
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Kirk Yap , James D. Guilford , Simon N. Peffers , Vinodh Gopal
IPC: G06F12/084 , G06F17/30 , G06F13/16 , G06F3/06
CPC classification number: G06F12/084 , G06F3/0629 , G06F13/1652 , G06F13/1668 , G06F16/2453 , G06F2212/621
Abstract: Various systems and methods for hardware acceleration circuitry are described. In an embodiment, circuitry is to perform 1-bit comparisons of elements of variable M-bit width aligned to N-bit width, where N is a power of 2, in a data path of P-bit width. Second and subsequent scan stages use the comparison results from the previous stage to perform 1-bit comparison of adjacent results, so that each subsequent stage results in a full comparison of element widths double that of the previous stage. A total number of stages required to scan, or filter, M-bit elements in N-bit width lanes is equal 1+log 2(N), and the total number of stages required for implementation in the circuitry is 1+log 2(P), where P is the maximum width of the data path comprising 1 to P elements.
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3.发明申请公开(公告)号：US20180234258A1
公开(公告)日：2018-08-16
申请号：US15434194
申请日：2017-02-16
Applicant: Intel Corporation
Inventor： Simon N. Peffers , Sean M. Gulley , Vinodh Gopal , Sanu K. Mathew
CPC classification number: H04L63/0428 , G06F1/04 , G06F16/00 , G09C1/00 , H04L9/0866 , H04L63/0876
Abstract: In one embodiment, an apparatus includes: a device having a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal; a controller coupled to the device, the controller to send the at least one control signal to the PUF circuit and to receive a plurality of PUF samples from the PUF circuit; a buffer having a plurality of entries each to store at least one of the plurality of PUF samples; and a filter to filter the plurality of PUF samples to output a filtered value, wherein the controller is to generate a unique identifier for the device based at least in part on the filtered value. Other embodiments are described and claimed.
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公开(公告)号：US11728665B2
公开(公告)日：2023-08-15
申请号：US17232023
申请日：2021-04-15
Applicant: Intel Corporation
Inventor： Naoki Matsumura , Simon N. Peffers , Steven Lloyd , Michael T. Crocker , Aaron Gorius
IPC: H02J7/00
CPC classification number: H02J7/0048 , H02J7/00714
Abstract: In some examples, a control unit is configured to adjust charge termination voltage of a rechargeable energy storage device. The control unit is adapted to charge the rechargeable energy storage device to a charge termination voltage where the rechargeable energy storage device has capacity to support peak load but comes close to a system shutdown voltage after supporting peak load. The control unit is also adapted to increase the charge termination voltage if a voltage of the rechargeable energy storage device is near a system shutdown voltage after supporting peak load.
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公开(公告)号：US10761877B2
公开(公告)日：2020-09-01
申请号：US15884259
申请日：2018-01-30
Applicant: Intel Corporation
Inventor： Simon N. Peffers , Sean M. Gulley
Abstract: Methods and apparatuses relating to accelerating blockchain transactions are described. In one embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction, and the hardware accelerator includes a dispatcher circuit to route the operation to a transaction processing circuit when the operation is a transaction operation and route the operation to a block processing circuit when the operation is a block operation. In another embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction; and a network interface controller including a dispatcher circuit to route the operation to a transaction processing circuit of the hardware accelerator when the operation is a transaction operation and route the operation to a block processing circuit of the hardware accelerator when the operation is a block operation.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190305797A1
公开(公告)日：2019-10-03
申请号：US16445556
申请日：2019-06-19
Applicant: Intel Corporation
Inventor： Simon N. Peffers , Vinodh Gopal , Kirk Yap
IPC: H03M7/30 , G06F12/0888 , G06F12/0875
Abstract: In one embodiment, an apparatus includes: a compression circuit to compress data blocks of one or more traffic classes; and a control circuit coupled to the compression circuit, where the control circuit is to enable the compression circuit to concurrently compress data blocks of a first traffic class and not to compress data blocks of a second traffic class. Other embodiments are described and claimed.
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公开(公告)号：US20190102837A1
公开(公告)日：2019-04-04
申请号：US15720514
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Ned M. Smith , Rajesh Poornachandran , Michael Nolan , Simon N. Peffers
Abstract: Various systems and methods for exchanging digital information in an online competitive data market and exchange network are disclosed. A buyer utilizes one or more curry functions that are relevant to data to be acquired thereby developing a Future estimate for the data. The Future estimate may be recorded as a Margin Future with an escrow agent acting as an intermediary with investors. Investors may fund the Margin Future based on assessed risk and return on investment as defined in the Margin Future. Once funded, the buyer may acquire the data from the seller and apply value to the data by applying the curry functions, to result in digital information to be traded on the online exchange. Once the Future has been realized by sales to information consumers, the market may distribute the proceeds/profits among the seller, buyer, investor and escrow agent, according to conditions defined in the Margin Future.
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公开(公告)号：US11836721B2
公开(公告)日：2023-12-05
申请号：US16024676
申请日：2018-06-29
Applicant: INTEL CORPORATION
Inventor： Ned M. Smith , Rajesh Poornachandran , Michael Nolan , Simon N. Peffers
IPC: G06Q20/40 , G06Q20/22 , G06Q20/38 , H04L9/06 , H04L9/32 , H04W56/00 , G06F16/23 , H04L9/00 , G06F21/64
CPC classification number: G06Q20/401 , G06F16/2379 , G06Q20/223 , G06Q20/389 , G06Q20/4016 , H04L9/0637 , H04L9/0643 , H04L9/3239 , H04L9/3297 , H04W56/001 , G06Q2220/00 , H04L9/50 , H04L2209/56 , H04L2209/805
Abstract: In some examples, an apparatus uses a blockchain to agree on a time in an information exchange network. A first node includes a processor communicatively coupled to a storage device including instructions. When executed by the processor, the instructions cause the processor to verify a time estimate from each of one or more other node, to determine a time match of a time estimate of the first node with the time estimates from the one or more other node, and if the time match is determined, to commit to the blockchain a transaction that includes a time stamp.
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公开(公告)号：US20210234377A1
公开(公告)日：2021-07-29
申请号：US17232023
申请日：2021-04-15
Applicant: Intel Corporation
Inventor： Naoki Matsumura , Simon N. Peffers , Steven Lloyd , Michael T. Crocker , Aaron Gorius
IPC: H02J7/00
Abstract: In some examples, a control unit is configured to adjust charge termination voltage of a rechargeable energy storage device. The control unit is adapted to charge the rechargeable energy storage device to a charge termination voltage where the rechargeable energy storage device has capacity to support peak load but comes close to a system shutdown voltage after supporting peak load. The control unit is also adapted to increase the charge termination voltage if a voltage of the rechargeable energy storage device is near a system shutdown voltage after supporting peak load.
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10.发明授权公开(公告)号：US10462110B2
公开(公告)日：2019-10-29
申请号：US15434194
申请日：2017-02-16
Applicant: Intel Corporation
Inventor： Simon N. Peffers , Sean M. Gulley , Vinodh Gopal , Sanu K. Mathew
Abstract: In one embodiment, an apparatus includes: a device having a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal; a controller coupled to the device, the controller to send the at least one control signal to the PUF circuit and to receive a plurality of PUF samples from the PUF circuit; a buffer having a plurality of entries each to store at least one of the plurality of PUF samples; and a filter to filter the plurality of PUF samples to output a filtered value, wherein the controller is to generate a unique identifier for the device based at least in part on the filtered value. Other embodiments are described and claimed.
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