Invention Grant
- Patent Title: Multi-layer passivation structure and method
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Application No.: US16395435Application Date: 2019-04-26
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Publication No.: US11145564B2Publication Date: 2021-10-12
- Inventor: Chih-Fan Huang , Hui-Chi Chen , Kuo-Chin Chang , Dian-Hau Chen , Yen-Ming Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/29 ; H01L23/00 ; H01L21/56

Abstract:
Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
Public/Granted literature
- US20200006183A1 Multi-Layer Passivation Structure and Method Public/Granted day:2020-01-02
Information query
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