公开(公告)号：US11855022B2

公开(公告)日：2023-12-26

申请号：US17854840

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/06 ,  H01L21/4814 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/5223 ,  H01L24/02 ,  H01L24/05 ,  H01L24/07 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05015 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US20210091029A1

公开(公告)日：2021-03-25

申请号：US17114112

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US10861810B2

公开(公告)日：2020-12-08

申请号：US16392024

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US11450588B2

公开(公告)日：2022-09-20

申请号：US16654198

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin Chi ,  Chien-Hao Hsu ,  Kuo-Chin Chang ,  Cheng-Nan Lin ,  Mirng-Ji Lii

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a substrate. The method includes forming a heat-spreading wall structure over the substrate. The heat-spreading wall structure is adjacent to the chip, and there is a first gap between the chip and the heat-spreading wall structure. The method includes forming a first heat conductive layer in the first gap. The method includes forming a second heat conductive layer over the chip. The method includes disposing a heat-spreading lid over the substrate to cover the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.

公开(公告)号：US11848270B2

公开(公告)日：2023-12-19

申请号：US16422988

申请日：2019-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Seng Shue ,  Sheng-Han Tsai ,  Kuo-Chin Chang ,  Mirng-Ji Lii ,  Kuo-Ching Hsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/023 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02235 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/081 ,  H01L2224/0805 ,  H01L2224/08052 ,  H01L2224/08113 ,  H01L2224/16104

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

公开(公告)号：US20200006183A1

公开(公告)日：2020-01-02

申请号：US16395435

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

公开(公告)号：US20220328440A1

公开(公告)日：2022-10-13

申请号：US17854840

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US11380639B2

公开(公告)日：2022-07-05

申请号：US17114112

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US11189538B2

公开(公告)日：2021-11-30

申请号：US16411529

申请日：2019-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Mao-Nan Wang ,  Kuo-Chin Chang ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

公开(公告)号：US20200168574A1

公开(公告)日：2020-05-28

申请号：US16392024

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L23/522

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.